QCA Based Design of Reversible Parity Generator and Parity Checker Circuits for Telecommunication

Abstract

Quantum-dot cellular automation (QCA) is a transistor-free technology used to implement nanoscale circuit designs. When compared to the widely used complementary metal oxide semiconductor (CMOS) technology, QCA circuits are faster, denser, and use less energy. It has some advantages in reversible logic, including its small size and low power dissipation. In this work, a model of a low-power 3-bit odd parity generator and checker circuit based on a reversible Feynman gate with 23 cells and 40 cells, respectively, is proposed. The proposed reversible odd parity generator and checker circuit can be used in telecommunication systems for bit loss detection and checking. The proposed circuits and the theoretical values are tested using QCA Designer simulator version 2.0.3 to ensure that the circuit works properly, and QCA Designer-E is used to estimate the energy dissipation of the circuits. According to the simulation results, the proposed circuits improve cell counts by 28% for the parity generator, 40% for the parity checker, and 27% for the nano-communication, and occupied area by 72% for the parity generator, 23% for the parity checker, and 14% for the nano-communication.