Enhancement of a Synthesized Single Cycle MIPS Processor on Altera DE2 FPGA Development Board

Abstract

The MIPS processor continues to be one of the most popular
processors in the field of embedded systems mainly because of its
speed and reduced instructions. This work presents a single cycle
MIPS synthesized on Altera DE2 development board. It is further
enhanced by developing extra sets of instructions. The design is
tested by running Mips Assembly Language (MAL) programs on the
model. Results indicate that the enhanced model has more
executable instructions and has an on board maximum frequency of
25MHz which is good for softcore processor.